Digital layout scan questions & answers. 1) Explain draw near setup organize and hold back organize, what intent chance if there is setup organize and hold back tine breach, how to defeat this? Set up organize is the amount of organize ahead the clock vehemence that the input signal needs to be faithful to guaranty it is accepted becomingly on the clock vehemence. Hold organize is the amount of organize after the clock vehemence that unvarying input signal has to be held ahead changing it to purloin responsible it is sensed becomingly at the clock vehemence. Whenever there are setup and hold back organize violations in any flip-flop, it enters a country where its lay out is unpredictable: this country is known as metastable country (quasi faithful state); at the vanish of metastable country, the flip-flop settles down to either ‘1′ or ‘0′.
This whole kit method is known as metastability 2) What is skew, what are problems associated with it and how to clip it? In ambit layout, clock skew is a occurrence in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at distinguishable components at distinguishable times. The inauguration is a textile divided, which causes a signal to touring faster or slower than expected. This is typically scheduled to two causes. The stand by is hesitation: if the signal has to touring the undamaged eventually of a ambit, it intent judicious (depending on the circuit’s size) appear at distinguishable parts of the ambit at distinguishable times. Clock skew can originator iniquity in two ways. Suppose that a reasonableness direction travels into done with combinational reasonableness from a well-spring flip-flop to a object flip-flop.
This is called a hold back breach because the past statistics is not held crave ample stock at the object flip-flop to be becomingly clocked into done with. If the object flip-flop receives the clock tick later than the well-spring flip-flop, and if the reasonableness direction lay impolitic is brief ample stock, then the statistics signal authority appear at the object flip-flop ahead the clock tick, destroying there the past statistics that should give birth to been clocked into done with. If the object flip-flop receives the clock tick earlier than the well-spring flip-flop, then the statistics signal has that much less organize to reach the object flip-flop ahead the next clock tick.
If it fails to do so, a setup breach occurs, misdesignated because the brand-new statistics was not break the ice up and faithful ahead the next clock tick arrived. A hold back breach is more fooling than a setup breach because it cannot be agreed beside increasing the clock age. It can be intentionally introduced to cut down the clock age at which the ambit intent direct correctly, and/or to escalating the setup or hold back safe keeping margins.
Clock skew, if done get even for, can also profit a ambit. The optimal break the ice of clock delays is decided beside a linear program, in which a setup and a hold back constraint appears in favour of each reasonableness direction. In this linear program, zero clock skew is unmistakably a workable blotch. Clock skew can be minimized beside undiluted routing of clock signal (clock parceling antiquated tree) or putting mercurial lay impolitic buffer so that all clock inputs appear at the unvarying organize 3) What is abate? ‘Slack’ is the amount of organize you give birth to that is intentional from when an anyway in the Aristotelianism entelechy ‘actually happens’ and when it ‘must happen’.. When something ‘must happen’ can also be called a ‘deadline’ so another delimitation of abate would be the organize from when something ‘actually happens’ (call this Tact) until the deadline (call this Tdead). The appellation ‘actually happens’ can also be enchanted as being a predicted organize in favour of when the anyway in the Aristotelianism entelechy intent ‘actually happen’. Slack = Tdead - Tact.
Negative abate implies that the ‘actually happen’ organize is later than the ‘deadline’ organize.in other words it’s too tardily and a timing breach..you give birth to a timing mind-boggler that needs some limelight. 4) What is glitch? What causes it (explain with waveform)? How to defeat it? The following lay faith in b map out on shows a synchronous opting for to the gated clock using a statistics direction. When the agree to is Low, the multiplexer feeds the lay out of the record backside on itself. The flip-flop is clocked at every clock progression and the statistics direction is controlled beside an agree to. When the agree to is High, brand-new statistics is fed to the flip-flop and the record changes its country 5) Given sole two xor gates Possibly man ought to assignment as buffer and another as inverter? Tie Possibly man of xor gates input to 1 it intent law as inverter.
Tie Possibly man of xor gates input to 0 it intent law as buffer. 6) What is change between latch and flipflop? The warble change between latch and FF is that latches are level impolitic delicate while FF are vehemence delicate. For a latch, the lay out tracks the input when the clock signal is far up, so as crave as the clock is reasonableness 1, the lay out can inescapable cash if the input also changes. They both be lacking the from of clock signal and are Euphemistic pre-owned in consecutive reasonableness. FF on the other shackles, intent rely on the input sole when there is a rising/falling vehemence of the clock. 7) Build a 4:1 mux using sole 2:1 mux? Difference between harvest and collect? The Stack is more or less leading in favour of keeping apprehend of what’s executing in our criterion criteria (or what’s been “called”).
The Heap is more or less leading in favour of keeping apprehend of our objects (our statistics, by a long way. Think of the Stack as a series of boxes stacked Possibly man on ace of the next. most of it - we’ll get someone’s goat to that later.).
We adhere to apprehend of what’s comfortable on in our steadfastness beside stacking another carton on ace every organize we dial a method (called a Frame). We can sole from what’s in the ace carton on the collect. When we’re done with the ace carton (the method is done executing) we emit it away and proceed to from the shit in the past carton on the ace of the collect. With the Heap, there are no constraints as to what can be accessed like in the collect. The Heap is comparable except that its inflexibility is to hold back facts (not adhere to apprehend of art most of the time) so anything in our Heap can be accessed at any organize. The Heap is like the harvest of exclusively laundry on our bed that we give birth to not enchanted the organize to lay away moreover - we can segment what we demand hastily.
The Stack is like the collect of shoe boxes in the closet where we give birth to to sponsor impolitic the ace Possibly man to get someone’s goat to the Possibly man underneath it. 9) Difference between mealy and moore country appliance? A) Mealy and Moore models are the uncomplicated models of country machines. A country appliance which uses sole Input Actions, so that the lay out depends on the country and also on inputs, is called a Mealy ideal. A country appliance which uses sole Entry Actions, so that its lay out depends on the country, is called a Moore ideal. The models selected intent change a layout but there are no all-inclusive indications as to which ideal is more wisely.
Choice of a ideal depends on the steadfastness, art means (for example, armaments systems are predominantly best clothes realized as Moore models) and familiar preferences of a artist or programmer B) Mealy appliance has outputs that depend on the country and input (thus, the FSM has the lay out written on edges) Moore appliance has outputs that depend on country sole (thus, the FSM has the lay out written in the country itself. Adv and Disadv In Mealy as the lay out mercurial is a assignment both input and country, changes of country of the country variables intent be delayed with relation to changes of signal level impolitic in the input variables, there are possibilities of glitches appearing in the lay out variables. All of the concepts can be applied to Moore-model country machines because any Moore country appliance can be implemented as a Mealy country appliance, although the chat is not correct. Moore overcomes glitches as lay out dependent on sole states and not the input signal level impolitic.
Moore appliance: the outputs are properties of states themselves. which means that you get someone’s goat the lay out after the appliance reaches a fact country, or to get someone’s goat some lay out your appliance has to be enchanted to a country which provides you the lay out.The outputs are held until you go close to some other country Mealy appliance: Mealy machines sponge you outputs instantly, that is directly upon receiving input, but the lay out is not held after that clock progression. 10) Difference between onehot and binary encoding? Common classifications Euphemistic pre-owned to greasepaint the country encoding of an FSM are Binary (or by a long way encoded) and One burning. The donation loads of flip-flops required is the unvarying to the ceiling of the log-base-2 of the loads of states in the FSM. A binary-encoded FSM layout sole requires as diverse flip-flops as are needed to uniquely encode the loads of states in the country appliance. A onehot FSM layout requires a flip-flop in favour of each country in the layout and sole Possibly man flip-flop (the flip-flop representing the overflowing or “hot” state) is break the ice at a organize in a Possibly man burning FSM layout. For a country appliance with 9- 16 states, a binary FSM sole requires 4 flip-flops while a onehot FSM requires a flip-flop in favour of each country in the layout FPGA vendors diverse a organize promote using a onehot country encoding form because flip-flops are fecund in an FPGA and the combinational reasonableness required to carry antiquated a onehot FSM layout is typically smaller than most binary encoding styles.
Since FPGA execution is typically reciprocal to the combinational reasonableness appraise of the FPGA layout, onehot FSMs typically come across faster than a binary encoded FSM with larger combinational reasonableness blocks 11) What are distinguishable ways to synchronize between two clock domains? 12) How to add up crack operating frequency? 13) How to arouse antiquated longest direction? You can arouse promoter to this in timing.ppt of presentations leg on this placement 14) Draw the country diagram to lay out a “1″ in favour of Possibly man progression if the modus operandi “0110″ shows up (the unsurpassed 0s cannot be Euphemistic pre-owned in more than Possibly man sequence)? 15)How to reach 180 deree enjoin angle party? Never advise using inverter a) dcm’s an inbuilt resource in most of fpga can be configured to get someone’s goat 180 to a considerable capaciousness angle party. 16) What is meaning of ras and cas in SDRAM? SDRAM receives its beat hold back forwards from the beginning to the end of in two beat words. b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be Euphemistic pre-owned. It uses a multiplex move to prevent input pins. The inauguration beat designation is latched into the DRAM interpose with the quarrel beat strobe (RAS).
Following the RAS hold back forwards from the beginning to the end of is the column beat strobe (CAS) in favour of latching the stand by beat designation. 17) Tell some of applications of buffer? a)They are Euphemistic pre-owned to initiate insignificant delays b)They are Euphemistic pre-owned to liquidate irascible talk caused scheduled to inter electrode capacitance scheduled to close routing. Shortly after the RAS and CAS strobes, the stored statistics is valid in favour of reading. c)They are Euphemistic pre-owned to stand by far up fanout,eg:bufg 1 Implement an AND audience using mux? This is the uncomplicated challenge that diverse interviewers ask about after. in favour of and audience, sponge Possibly man input as opt for hawser,incase if u r giving b as opt for hawser, mix Possibly man input to reasonableness ‘0′ and other input to a. 19) What intent chance if contents of record are shifter anchorage side, get even for? It is by a long way known that in anchorage side party all bits intent be shifted anchorage side and LSB intent be appended with 0 and in get even for party all bits intent be shifted get even for and MSB intent be appended with 0 this is a straightforward promoter What is expected is in a anchorage side party value gets Multiplied beside 2 eg:consider 0000_1110=14 a anchorage side party intent purloin it 0001_110=28, it the unvarying composition get even for party intent Divide the value beside 2. Therefore, FIFO appraise = 3000ns/40ns = 75 entries 21) Design a four-input NAND audience using sole two-input NAND gates.
20)Given the following FIFO and rules, how antiquated of the curious does the FIFO demand to be to stave off underflow or overflow? RULES: 1) frequency(clk_A) = frequency(clk_B) / 4 2) period(en_B) = period(clk_A) * 100 3) duty_cycle(en_B) = 25% Assume clk_B = 100MHz (10ns) From (1), clk_A = 25MHz (40ns) From (2), period(en_B) = 40ns * 400 = 4000ns, but we sole lay out in favour of 1000ns,due to (3), so 3000ns of the agree to we are doing no lay out composition. A:Basically, you can tether the inputs of a NAND audience together to get someone’s goat an inverter, so. 22)Difference between Synchronous and Asynchronous reset.? Synchronous reset reasonableness intent synthesize to smaller flip-flops, distinctively if the reset is gated with the reasonableness generating the d-input.
But in such a at all events, the combinational reasonableness audience absolute grows, so the complete audience absolute savings may not be that meritorious. In some designs, the reset ought to be generated beside a break the ice of internal conditions. The clock works as a divided in favour of insignificant reset glitches; putting, if these glitches make one ruminate over itself to draw near the functioning clock vehemence, the Flip-flop could go close metastable.
A synchronous reset is recommended in favour of these types of designs because it intent divided the reasonableness equation glitches between clock. Disadvantages of synchronous reset: Problem with synchronous resets is that the unifying composition cannot without difficulty suggestion the reset signal from any other statistics signal. Synchronous resets may demand a pulsation stretcher to guaranty a reset pulsation compass large ample stock to immune reset is donation during an functioning vehemence of the clock[ if you give birth to a gated clock to prevent power, the clock may be crippled coincident with the asseveration of reset. Designs that are pushing the limit in favour of statistics direction timing, can not deal out to give birth to added gates and additional clear delays in the statistics direction scheduled to reasonableness inserted to buy and deliver up synchronous resets. Only an asynchronous reset intent composition in this setting, as the reset authority be removed until to the resumption of the clock.
Asynchronous reset in the warble: The biggest mind-boggler with asynchronous resets is the reset shift loose, also called reset house-moving. Using an asynchronous reset, the artist is guaranteed not to give birth to the reset added to the statistics direction. Another advancement favoring asynchronous resets is that the ambit can be reset with or without a clock donation. if the shift loose of the reset occurred on or draw near a clock vehemence such that the flip-flops went metastable. Disadvantages of asynchronous reset: immune that the shift loose of the reset can make one ruminate over itself to within Possibly man clock age. 23) Why are most interrupts functioning little? This answers why most signals are functioning little If you approximate the transistor level impolitic of a module, functioning little means the capacitor in the lay out terminating gets charged or discharged based on little to far up and far up to little transmutation individually.
when it goes from far up to little it depends on the drawing down resistor that pulls it down and it is less expansive in favour of the lay out capacitance to execution degree than charging. this persuade people choose using functioning little signals. (b) Connect the lay out to Possibly man of the input and the other to the input signal.
24)Give two ways of converting a two input NAND audience to an inverter? (a) brief the 2 inputs of the nand audience and force the distinct input to it. 25) What are break the ice up organize & hold back organize constraints? What do they important? Which Possibly man is deprecative in favour of estimating crack clock frequency of a ambit? break the ice up organize: - the amount of organize the statistics should be faithful ahead the steadfastness of the clock signal, where as the hold back organize is the amount of organize the statistics should be faithful after the steadfastness of the clock. Setup organize signifies crack lay impolitic constraints; hold back organize is in favour of littlest lay impolitic constraints. Setup organize is deprecative in favour of establishing the crack clock frequency. Flip-flops are made up of latches.
26) Differences between D-Latch and D flip-flop? D-latch is level impolitic delicate where as flip-flop is vehemence delicate. 27) What is a multiplexer? Is combinational ambit that selects binary facts from Possibly man of diverse input lines and directs it to a distinct lay out hawser. (2n =>n).
28)How can you proselyte an SR Flip-flop to a JK Flip-flop? By giving the dine backside we can proselyte, i.e in the warble!Q=>S and Q=>R.Hence the S and R inputs intent law as J and K individually. 30)What is Race-around mind-boggler?How can you break the ice get even for it? The clock pulsation that remains in the 1 country while both J and K are the unvarying to 1 intent originator the lay out to embody antiquated again and duplication complementing until the pulsation goes backside to 0, this is called the racecourse in every operation mind-boggler.To circumvent this unwanted efficacious, the clock pulsation ought to give birth to a organize duration that is shorter than the propagation lay impolitic organize of the F-F, this is restrictive so the opting for is master-slave or edge-triggered construction. 29)How can you proselyte the JK Flip-flop to a D Flip-flop? By connecting the J input to the K into done with the inverter. 31)How do you vouch for if two 8-bit signals are unvarying? XOR each bits of A with B (for e.g.
A[0] xor B[0] ) and so on.the o/p of 8 xor gates are then procumbent as i/p to an 8-i/p nor audience. if o/p is 1 then A=B. After how diverse clock cycles intent it takings to the first country? 6 cycles 33) Convert D-FF into split beside 2. 32)7 scintilla dialect knoll counter’s first country is 0100010.
(not latch) What is the max clock frequency the ambit can buy and deliver up, procumbent the following facts? T_setup= 6nS T_hold = 2nS T_propagation = 10nS Circuit: Connect Qbar to D and force the clk at clk of DFF and sponsor the O/P at Q. It gives freq/2. Max. Design all the uncomplicated gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer? Using 2:1 Mux, (2 inputs, 1 lay out and a opt for line) (a) NOT Give the input at the opt for hawser and mix I0 to 1 & I1 to 0. Freq of efficacious: 1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz 34)Guys this is the uncomplicated challenge asked most diverse a organize. So if A is 1, we intent get someone’s goat I1 that is 0 at the O/P. (b) AND Give input A at the opt for hawser and 0 to I0 and B to I1.
O/p is A & B (c) OR Give input A at the opt for hawser and 1 to I1 and B to I0. O/p intent be A in the warble B (d) NAND AND + NOT implementations together (e) NOR OR + NOT implementations together (f) XOR A at the opt for hawser B at I0 and ~B at I1.